Alchip Technologies Announces 3DFabric™ Alliance Support

Taipei, Taiwan, Feb. 01, 2023 (GLOBE NEWSWIRE) — Alchip Technologies is introducing its role as a founding member of TSMC’s 3DFabric™ alliance, advancing its 3nm process technology and advanced packaging capabilities.

The company supports the foundry initiative, which was announced in late October, as a market driver that will bring Alchip’s most advanced high-performance computing ASIC technology to leading customer applications.

TSMC 3DFabric is a comprehensive family of 3D silicon stacking and advanced packaging technologies that unlocks customer innovation in a system-level approach. It consists of TSMC’s front-end technologies, or TSMC-SoIC™ (System on Integrated Chips), special materials for 3D stacked die assembly and testing, and TSMC’s 3DFabric back-end technologies include the CoWoS and InFO family of packaging technologies.

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The TSMC 3DFabric Alliance is the latest addition to the TSMC Open Innovation Platform® (OIP). The new alliance partners have early access to TSMC’s 3DFabric technologies, allowing them to develop and optimize their solutions in parallel with TSMC. It provides customers with early access to EDA, IP, Memory, Outsourced Semiconductor Assembly and Test (OSAT), Substrate and Test.

“As a leader in high-performance computing ASICs, Alchip’s participation in the TSMC 3DFabric Alliance is a must,” said Johnny Shen, president and CEO of Alchip Technologies. “This new initiative strengthens TSMC’s semiconductor leadership, providing strategic opportunities for leading, high-performance ASIC companies to expand their state-of-the-art packaging capabilities for innovative technology customers.”

Alchip has developed a 3nm customer ASIC design and released its first test chip in January 2023. It became the first dedicated high-performance ASIC company to announce full design and manufacturing ecosystem readiness targeting TSMC’s latest N3E process technology.

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In advanced packaging, Alchip is fine-tuning its industry-leading chip to a more secure-on-substrate (CoWoS®) packaging option. CoWoS improves overall on-chip interconnect density and performance and is critical to almost every high-performance computing (HPC) ASIC.

CoWoS is a 2.5D wafer-level multi-chip packaging technology that includes adjacent shapes on a silicon intermediate. Micropads connect individual chips with a silicon spacer to form a chip on a wafer. Wrapping is completed by connecting to the base of the pack.

CoWoS chipsets include a high-performance system-on-chip (SoC) and a high-performance memory (HBM3 or HBM2E) unit. Alchip’s CoWoS service covers all types of CoWoS packages, such as CoWoS-S, CoWoS-R and CoWoS-L.

For more information about Alchip, visit

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About Alchipa

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global provider of silicon and design and manufacturing services to systems companies developing complex and high-volume ASICs and SoCs. The company provides faster time-to-market and cost-effective solutions for SoC design in conventional and advanced processes, including 7nm, 6nm, 5nm and 4nm processes. Alchip has built its reputation as a leader in high-performance ASICs through advanced 2.5D/3D package services, CoWoS/chiplet design and manufacturing expertise. Customers include world leaders in artificial intelligence, HPC/supercomputing, mobile phones, entertainment devices, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661), is a TSMC-certified value chain assembler, and is a founding member of the new TSMC 3DFabric Alliance®.

  • Examples of CoWoS chipsets



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